The present invention relates to integrated circuit technology. More particularly, the present invention relates to logic blocks for integrated circuits, logic blocks for programmable integrated circuits, and particularly math blocks including both hard and soft logic. A math block is a circuit for computing mathematical operations, such as addition or multiplication.
Existing FPGA math blocks in field programmable gate array (FPGA) integrated circuits are composed exclusively of hard logic. While such math blocks may be somewhat configurable (for example, registers may be bypassed or multiplexers may be set to select one of two or more inputs), they cannot be used for general purposes to implement non-math portions of a target application.
FPGAs include “soft” logic which is general-purpose and highly programmable. Soft logic is usually composed of flip-flops and lookup tables (LUTs). Sometimes it also includes carry lookahead circuitry or simple gates such as AND gates, OR gates or multiplexers. Modern FPGAs usually also include “hard” logic that has a specific purpose and implements a fixed function, such as math or RAM block. The fixed function performed by these hard logic blocks may have a limited number of programmable operating modes.
Hard logic blocks obviously require connections to the general-purpose programmable routing. These connections allow the block inputs to receive signals from any portion of the soft logic anywhere in the chip, and the block outputs to drive any portion of the soft logic anywhere in the chip.
The hard logic is typically implemented using a standard cell library and/or custom layout. It is highly specialized to implement certain functions, and is of very limited or no use for other purposes. On the other hand, the soft logic is general purpose, and is useful to implement most any portion of the target application. However, when the hard logic can be used it is much more efficient in area, speed, and power than implementing the equivalent function in soft logic.
Three non-exhaustive examples of existing FPGA “hard” math blocks include the UltraScale+ Math Block in products including the DSP48E2 marketed by Xilinx, Inc., the Arria® 10 math block available from Intel, and a math block included in the ECP4 DSP Slice Architecture marketed by Lattice Semiconductor, and the math blocks provided in the RTAXD, SmartFusion2 and RTG4 FPGA families marketed by Microsemi. A prior art math block typically includes one or two multipliers, zero or more adders, and registers. The registers usually may be configured to be bypassed or not. The math block usually also includes multiplexers that may be configured to select one of their input busses. In addition to the inputs and outputs that connect the math block to the programmable routing, the math blocks have dedicated connections to adjacent math blocks that are not accessible to the general-purpose programmable routing.
As with all “hard” logic blocks, the math block function is largely fixed and special purpose, with only limited configurability. It supports a limited range of math operations, and is not usable for general purposes to implement non-math portions of a target application. When a hard block is not used, the area it occupies and the static power it consumes are wasted. Furthermore, the portion of the capacity of the general-purpose routing network that supports the inputs and outputs of the block is wasted.
A way to reclaim some value from this unused routing capacity is described in Peter Jamieson and Jonathan Rose, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 18, No. 12, December 2010. The authors propose an architecture in which the connections to the programmable routing used for a hard logic block (such as a math block) are shared with some soft logic, which they call “shadow” logic. Such an architecture is shown in FIG. 1 in which a hard logic block 10 is shown coupled to shared input routing resources 12 and shared output routing resources 14. Shadow soft logic 16 is also coupled to the shared input routing 12. The outputs of the hard logic block 10 and the shadow soft logic 16 are coupled to the shared output routing resources 14 through a shadow multiplexer 18. The idea is that if the hard logic block 10 is not used, the shadow soft logic 16 can be used for general purposes instead by using shadow multiplexer 18 to connect the output of shadow soft logic 16, instead of the output of hard logic block 10, to the shared output routing resources 14. This avoids wasting the scarce and expensive programmable routing capacity of the shared input and output routing resources 12 and 14 required to service the hard logic block 10. However, in this approach the use of the shadow soft logic 16 and the hard logic block 10 is mutually exclusive. If the hard logic block 10 is used, the shadow soft logic 16 is unselected by the multiplexer 18, cannot be used, and thus is wasted.
Over time, hard math blocks have become more complex. Besides the basic functionality of a multiplier and final adder/accumulator, they may require supplementary functionality such as a pre-adder, register chains, additional multiplexers (such as in the “booster logic” of the ECP4 DSP Lattice block) or even small RAMs to store coefficient values (as in the Intel Arria® 10 math block). This supplementary functionality is needed in some but not all modes of operation of the math block. In the prior art, this supplementary functionality is provided by adding additional hard logic circuitry to the math block. However if the math block is not used, or if the math block is used but in a mode that does not require the supplementary functionality, the area occupied by the additional hard circuitry and the static power it consumes are wasted.
In theory, it would be possible to implement the supplementary functionality using soft logic. However this is problematic. Since the connections between the soft and hard logic go through the general-purpose routing, they may have varying delays that are slow and difficult to predict. This make it difficult to ensure that the combination of the basic and supplementary functionality operates at the necessary speed.
Thus, it would be desirable to (a) get some value from the shadow soft logic even when the hard block is used, and/or (b) provide the supplementary functionality that may be needed for certain modes of the hard block in a more efficient way than providing additional hard logic circuitry.